QuickSilicon
AutomatedHands-on hardware design and verification courses covering RTL, RISC-V, and testbench design.
QuickSilicon has 7 plans: a free plan and paid plans from $20. We have not recorded a price change.
QuickSilicon plans and prices
21 Days of RTL
$0
- one-time$0 one-time(Free)
- monthly$0/mo($0)
- Various SystemVerilog language constructs useful for writing modern synthesizable RTL
- Learn, develop and share RTL Design and Testbenches
- Start from a basic mux to designing round-robin arbiters
- Get working solutions in SystemVerilog
SystemVerilog for Design
one time$20
- one-time$20 one-time($20)
- monthly$20/mo($20)
- Various SystemVerilog language constructs useful for writing modern synthesizable RTL
- Understanding how sequential and combinatorial logic is converted into RTL
- Get exposed to converting microarchitecture to RTL
- Learn basic building-blocks like counters, shift-registers from ground up
VIPT Cache Design
one time$35
- one-time$35 one-time($35)
- monthly$35/mo($35)
- Start from Specification and build microarchitecture and RTL
- 3-stage Pipelined design
- SKY130 SRAM Macros
- LRU Replacement Policy
- SystemVerilog for RTL Design
- 3-day no question asked return policy
Hands-On RTL Design for Networking Systems
one time$35
- one-time$35 one-time($35)
- monthly$35/mo($35)
- Problemset specialized in design patterns from the world of networking chips
- Directly inspired by real world silicon and big tech interview questions
- Covers various sub-topics ranging from simple gearboxes to complex packet parsers, arbiters and timing logic
- Power, performance and area tradeoffs to be handled in each problem
- Course is available only in System Verilog
Hands-on Testbench Design
one time$50
$50 (pre-launch discounted price)
- one-time$50 one-time($50 (pre-launch discounted price))
- monthly$50/mo($50)
- SystemVerilog verification constructs
- Build complete testbench with DPI support for RV32I RISC-V
- Video explanations and working solutions
- 3-day no-questions-asked refund policy
Hands-on RTL Design
one time$60
- one-time$60 one-time($60)
- monthly$60/mo($60)
- 25 handpicked questions to up your interview game
- Learn about skid buffers, fifos, valid-ready protocol and a lot more
- Designing complex microarchitectures with focus on PPA
- Converting microarchitecture details into real-world synthesizable RTL
- Various industry standard timing optimisation challenges
RISC-V Processor Design
one time$80
- one-time$80 one-time($80)
- monthly$80/mo($80)
- RV32I unprivileged RISC-V ISA
- Design a single-cycle RV32I processor from scratch
- Write and execute RISC-V assembly programs
- 3-day no-questions-asked refund policy
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