QuickSilicon

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Hands-on hardware design and verification courses covering RTL, RISC-V, and testbench design.

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Total changes

Last change

Jul 14, 2026

Price trend

Current pricing

21 Days of RTL

one time

Free

SystemVerilog language constructs for synthesisable RTL
Learn and share RTL design and testbenches
Working solutions in SystemVerilog

SystemVerilog for Design

one time

$20/one_time

$20

SystemVerilog constructs for synthesisable RTL
Sequential and combinatorial logic to RTL

Price history

Last 14 changes

Date	Plan	Change	Old	New	Δ%

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3-day no-questions-asked refund policy

VIPT Cache Design

one time

$35/one_time

$35

Build microarchitecture and RTL from spec
3-stage pipelined design
SKY130 SRAM macros, LRU replacement policy
3-day no-questions-asked refund policy

Hands-On RTL Design for Networking Systems

one time

$35/one_time

$35

Design patterns from real networking chips
Gearboxes, packet parsers, arbiters, timing logic
3-day no-questions-asked refund policy

Hands-on Testbench Design

one time

$50/one_time

$50 (pre-launch discounted price)

SystemVerilog verification constructs
Build complete testbench with DPI support for RV32I RISC-V
Video explanations and working solutions
3-day no-questions-asked refund policy

Hands-on RTL Design

one time

$60/one_time

$60

25 handpicked interview-style questions
Skid buffers, FIFOs, valid-ready protocol
Microarchitecture with focus on PPA
3-day no-questions-asked refund policy

RISC-V Processor Design

one time

$80/one_time

$80

RV32I unprivileged RISC-V ISA
Design a single-cycle RV32I processor from scratch
Write and execute RISC-V assembly programs
3-day no-questions-asked refund policy

Last deploy main@a1b2c3d

Jul 14, 2026	RISC-V Processor Design	new plan	—	$80	—
Jul 14, 2026	Hands-on RTL Design	new plan	—	$60	—
Jul 14, 2026	Hands-on Testbench Design	new plan	—	$50	—
Jul 14, 2026	Hands-On RTL Design for Networking Systems	new plan	—	$35	—
Jul 14, 2026	VIPT Cache Design	new plan	—	$35	—
Jul 14, 2026	SystemVerilog for Design	new plan	—	$20	—
Jul 14, 2026	21 Days of RTL	new plan	—	$0	—
Jul 14, 2026	RISC-V Processor Design	new plan	—	$80	—
Jul 14, 2026	Hands-on RTL Design	new plan	—	$60	—
Jul 14, 2026	Hands-on Testbench Design	new plan	—	$50	—
Jul 14, 2026	Hands-On RTL Design for Networking Systems	new plan	—	$35	—
Jul 14, 2026	VIPT Cache Design	new plan	—	$35	—
Jul 14, 2026	SystemVerilog for Design	new plan	—	$20	—
Jul 14, 2026	21 Days of RTL	new plan	—	$0	—